The development of integrated circuits, such as processors or memories, is driven by the increasing miniaturization of the minimum feature sizes of the components. The density of components on a semiconductor substrate, such as a silicon wafer, can be increased by reducing the minimum feature sizes, such as for example a channel length of a transistor, which in turn leads to lower costs per chip. When reducing the minimum feature sizes, it is particularly important to produce structures with openings of a low aspect ratio, i.e., a low ratio between a height of the opening and a width of a basic surface area (also referred to below as the footprint or contact surface) of the opening, in order to satisfy for example demands relating to the minimum required capacitance and also with regard to mechanical stability of storage capacitors designed as stacked capacitors in dynamic random access memories (DRAMs).
Structures with openings with a low aspect ratio also allow a low contact resistance at contact holes. In both cases, openings with a low aspect ratio are desirable in order to achieve the largest possible contact surface to the pre-processed semiconductor substrate lying beneath the structure, in the case of DRAMs with a stacked capacitor on account of the required mechanical stability of free-standing, for example cylindrical structures which occur during the process sequence of producing stacked capacitors, which on account of the capillary forces threaten to tilt over and come into contact with one another during a wet-chemical etch. A low contact resistance, for example to active components as a source/drain terminal, can also be achieved by using the largest possible contact surface to the pre-processed semiconductor substrate located beneath the structure, allowing fast switching times.
The publication “Effective Capacitance Enhancement Methods for 90-nm DRAM Capacitors”, Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pages 112-116, by Y.K. Park et al., proposes an OCS (one cylinder storage node) for improving mechanical stability during the production of stacked capacitors in DRAMs. In this case, two oxide layers, for example a BPSG (boron phosphorous silicate glass) layer and a PETEOS (plasma-enhanced tetra-ethyl-ortho-silicate) layer, are stacked on top of one another, and openings are introduced by anisotropic etching. A wet-chemical etching step is used to increase the contact surface to the semiconductor substrate formed beneath the two oxide layers.
For these and other reasons there is a need for the present invention.